1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to the structure of a signal and data input/output part of a dynamic semiconductor memory device.
2. Description of the Background Art
FIG. 30 schematically illustrates the overall structure of a conventional dynamic semiconductor memory device. Referring to FIG. 30, the semiconductor memory device is formed on a semiconductor chip 1 and includes four memory cell arrays 2a to 2d, each having a plurality of memory cells arranged in a matrix form. A row selection circuit (a row predecoder, a row decoder and a word line driver) and a column selection circuit (a column predecoder, a column decoder and an I/O gate) are provided in order to select memory cells in accordance with address signals, while these circuits are not shown for simplifying the figure. Each of the memory cell arrays 2a to 2d are divided into four column groups, and global I/O line pairs GIOP are arranged in correspondence to the respective column groups. In each of the memory cell arrays 2a to 2d, a 1-bit memory cell is selected in each column group, to be coupled with the global I/O line pair GIOP for the selected memory cell.
The semiconductor memory device further includes preamplifiers/write buffers 7 which are provided in correspondence to the global I/O line pairs GIOP respectively for inputting/outputting data in/from the corresponding global I/O line pairs GIOP, read drivers 8 which are provided in correspondence to the preamplifiers/write buffers 7 for amplifying internal read data received from the corresponding preamplifiers for transmission to corresponding read data buses RDAP (RDAPa to RDAPd), first test mode circuits 9 which are provided in correspondence to the memory cell arrays 2a to 2d respectively for discriminating coincidence/incoincidence of logics of data read from the preamplifiers of the corresponding memory cell arrays in a test operation mode, a second test mode circuit 10 which receives signals indicating the discrimination results from the first test mode circuits 9 provided for the memory cell arrays 2a to 2d respectively for discriminating coincidence/incoincidence of the logics of the received discrimination result signals, and a driver 11 which receives signals on the read data buses RDAPa to RDAPd and a signal from the test mode circuit 10 for selectively transmitting the received signals to an output buffer 13 through output bus RDP.
The preamplifiers/write buffers 7 select a column group in each of the memory cell arrays 2a to 2d, so that memory cell data of the selected column groups are transmitted onto the corresponding read data buses RDAPa to RDAPd through the read drivers 8. In the test operation mode, all of the four column groups are selected in each of the memory cell arrays 2a to 2d, so that output signals of the four preamplifiers 7 are transmitted to the corresponding first test mode circuit 9.
In a normal operation mode, the driver 11 selects read data from a selected memory cell array from those read on the read data buses RDAPa to RDAPd, and supplies the same to the output buffer 13. In the test operation mode, on the other hand, the driver 11 selects a signal indicating the test result from the test mode circuit 10 and transmits the same onto the output buffer 13. Write buffers of the preamplifiers/write buffers 7 are coupled to an input buffer 12 through an input data bus WD. The write buffer corresponding to a selected one of the memory cell arrays 2a to 2d is activated, so that data is written in a selected memory cells included in a selected column group through the write buffers in the selected memory cell array.
The semiconductor memory device further includes an address buffer 3 which receives an externally supplied address signal and generates an internal address signal, an ATD generation circuit 4 which detects a transition of the internal address signal (internal column address signal) received from the address buffer 3 and generates an address transition detection signal ATD, a PAE generation circuit 5 which generates a preamplifier enable signal PAE for activating preamplifiers included in the preamplifiers/write buffers 7 in response to the address transition detection signal ATD from the ATD generation circuit 4, and an IOEQ generation circuit 6 which generates an equalization instruction signal IOEQ for equalizing the global I/O line pairs GIOP in response to the address transition detection signal ATD from the ATD generation circuit 4. The global I/O line pairs GIOP, which are formed by complementary signal line pairs, transmit complementary data signals. Potentials of the global I/O lines of the global I/O line pairs GIOP are equalized to each other by the equalization signal IOEQ.
The semiconductor memory device further includes an internal voltage down converter (VDC) 29 which receives an externally supplied source potential Vcc and generates a peripheral circuit source potential Vccp and a memory cell array source potential Vccs which are lower than the external source potential Vcc. The peripheral circuit source potential Vccp is supplied to peripheral circuits such as the preamplifiers/write buffers 7 and the read drivers 8 as a first operation source potential. The memory cell array source potential Vccs is applied to circuits for driving the memory cell arrays 2a to 2d (sense amplifiers charging/discharging bit lines) and substrate regions of p-channel MOS transistors in the arrays, as described later in detail. The peripheral circuit source potential Vccp is supplied to bit line equalization circuits for equalizing bit lines and circuit parts generating cell plate potentials which are applied to cell plates of the memory cells (first source nodes of memory capacitors).
The input buffer 12 and the output buffer 13 are illustrated as inputting/outputting data from/to the exterior of the device through a common data input/output terminal DQ. This semiconductor device inputs/outputs 1-bit data. A multibit test operation which is related to the present invention is now described.
When the storage capacity of a semiconductor memory device is increased, the number of memory cells is also increased correspondingly. When defects/non defects of memory cells are decided in units of bits, the test time is extremely increased. Therefore, the test time is reduced by simultaneously deciding defects/non-defects of a plurality of memory cells. A mode of making a test in units of a plurality of memory cells is called a multibit test mode.
A test data write operation of the multibit test mode is described. A row of memory cells is selected in each of the memory cell arrays 2a to 2d. Then, 4-bit memory cells are selected in each of the memory cell arrays 2a to 2d. Test data to be written in the selected memory cells are transmitted from the input buffer 12 to the write buffers included in the preamplifiers/write buffers 7. In the multibit test mode, all write buffers are brought into operating states. Thus, the same test data are written in the 4-bit memory cells selected in each of the memory cell arrays 2a to 2d, so that the same test data are written in 16-bit memory cells in total.
A data read operation in the multibit test mode is now described. Similarly to the test data writing, 4-bit memory cells are simultaneously selected in each of the memory cells 2a to 2d. All preamplifiers included in the preamplifiers/write buffers 7 are brought into operating states. Data of the 4-bit memory cells selected in each of the memory cell arrays 2a to 2d are amplified by the preamplifiers, and transmitted to the corresponding first test mode circuits 9. The first test mode circuits 9 each discriminate coincidence/incoincidence of the logics of the supplied 4-bit memory cell data, and transmit signals indicating the results of the discrimination to the second test mode circuit 10. The second test mode circuit 10 discriminates whether or not coincidence of the logics is detected in every one of the four first test mode circuits 9, in accordance with the discrimination result indication signals received from the four first test mode circuits 9. A discrimination result indication signal of the test mode circuit 10 is supplied through the driver 11 to the output buffer 13, which in turn transmits the signal indicating the discrimination result to the data input/output terminal DQ. The second test mode circuit 10 discriminates whether or not the logics of the 4-bit memory cells selected in each of the memory cell arrays 2a to 2d, i.e., the data of 16-bit memory cells in total, coincide with each other. A determination is made as to whether or not the simultaneously selected 16-bit memory cells include a defective memory cell by observing the logic of the output signal from the second test mode circuit 10.
16-bit memory cells can be tested at the same time, whereby the test time can be remarkably reduced.
In the structure of the conventional semiconductor memory device, the first test mode circuits are provided in correspondence to the plurality of memory cell arrays respectively, while the output signals of the plurality of first test mode circuits are transmitted to the second test mode circuit so that defects/non-defects of the simultaneously selected memory cells is finally discriminated therein. In order to transmit signals from the first test mode circuits to the second test mode circuit, signal lines which are provided in paths independent of read data buses are employed. Therefore, an area occupied by interconnections for the test is disadvantageously increased.
FIG. 31 schematically illustrates the structure of a data write part. This figure typically shows a pair of bit lines BL and /BL and a sense amplifier which is formed by p-channel MOS transistors (insulated gate field-effect transistors) provided in correspondence thereto. The sense amplifier includes a p-channel MOS transistor PQa having a first conduction terminal (drain) connected to the bit line BL and a gate connected to the bit line /BL, a p-channel MOS transistor PQb having a first conduction terminal (drain) connected to the bit line /BL and a gate connected to the bit line BL, and a p-channel MOS transistor PQc which conducts in response to a sense amplifier activation signal .phi.SP and transmits the array source potential Vccs to second conduction terminals (sources) of the MOS transistors PQa and PQb. The bit lines BL and /BL are connected with memory cells, which are omitted for simplifying the figure. With respect to the bit lines BL and /BL, selection gates TGa and TGb are provided which conduct in response to a column selection signal Y for electrically connecting the bit lines BL and /BL to internal data lines IO and /IO respectively. The internal data lines IO and /IO are connected to a write buffer WB.
The write buffer WB, which is included in the preamplifier/write buffer, operates with the peripheral circuit source potential Vccp serving as a first operation source potential. The source potential Vccs and the peripheral circuit source potential Vccp which are supplied to the memory cell array part are generated by the internal voltage down converter 29 shown in FIG. 30. These source potentials are so separately generated that the source potential Vccp for the write buffer or the peripheral circuit remains unchanged and can stably drive the peripheral circuit even if a sense operation for memory cell data is performed in the array and the source potential Vccs fluctuates. When the peripheral circuit source potential Vccp fluctuates upon operation of the peripheral circuit, on the other hand, this fluctuation exerts no influence on the array source potential Vccs, and hence the array part is prevented from a malfunction.
The column selection signal Y, which is outputted from a column decoder included in the peripheral circuit, is at the peripheral circuit source potential Vccp level. In data writing, the column selection signal Y goes high, the column selection gates TGa and TGb conduct, and the bit lines BL and /BL are electrically coupled to the write buffer WB. The write buffer WB generates complementary write data from internal write data WD and transmits the same onto the internal data lines IO and /IO. Thus, the write data are transmitted to the bit lines BL and /BL. A number of memory cells are arranged in the memory cell array part, and the number of sense amplifiers is also increased in response (the sense amplifiers are arranged in correspondence to the respective columns (bit line pairs)). Therefore, current consumption is increased by charging/discharging of the bit lines in sense amplifier operations. Lowering of the array source potential Vccs is considered in order to reduce this current consumption.
FIG. 32 schematically illustrates the sectional structure of the p-channel MOS transistor PQa or PQb shown in FIG. 31. The MOS transistor PQa (or PQb) is formed by high concentration p-type impurity regions IDRa and IDRb which are formed separatedly from each other on a surface of a well region WEL provided by a low concentration n-type impurity region, and a gate electrode layer GEL which is formed on the surface of the well region WEL between the impurity regions IDRa and IDRb with a gate insulating film (not shown) interposed therebetween. The well region WEL is formed on a p-type semiconductor substrate SUB. The well region WEL receives the array source potential Vccs through a high concentration n-type impurity region IDRc. The semiconductor substrate SUB receives a substrate bias potential VBB (negative potential).
Consider that a signal of the source potential Vccp level is supplied from the write buffer WB to the impurity region IDRa. This well structure contains a vertical pnp parasitic bipolar transistor having an emitter, a base region and a collector which are defined by the impurity region IDRa, the well region WEL and the semiconductor substrate SUB respectively. When the source potential Vccp is lower than the array source potential Vccs, no current flows from the impurity region IDRa to the well region WEL since the base and the emitter of the parasitic bipolar transistor are reverse-biased, and this p-channel MOS transistor stably operates.
When the array source potential Vccs is reduced below the peripheral circuit source potential Vccp in order to reduce power consumption in the array part, however, the base and the emitter of the parasitic bipolar transistor are forward-biased and this parasitic bipolar transistor is brought into an ON state so that a current flows from the impurity region IDRa to the well region WEL and then from the well region WEL to the semiconductor substrate SUB, thereby disadvantageously increasing the substrate potential VBB of the semiconductor substrate SUB. Such increase of the substrate potential VBB leads to fluctuation of the threshold voltage of an n-channel MOS transistor formed in a portion which is not shown in the figure and formation of a parasitic MOS transistor which is formed under the signal lines, resulting in an instable internal operation. Therefore, the peripheral circuit source potential Vccp cannot be reduced below the array source potential Vccs. In this peripheral circuit part, the signal amplitude is reduced and data can be transferred at a high speed when the source potential Vccp is reduced, while the operating speed is slowed down upon reduction of the source potential (the operating speed of a MOS transistor is proportionate to the gate potential). The peripheral circuit source potential Vccp may conceivably be further reduced following reduction of the array source potential Vccs. When the peripheral circuit source potential Vccp is reduced following reduction of the array source potential Vccs for high-speed operability, however, the operating speed is disadvantageously reduced since the peripheral circuit source potential is supplied not only to the write buffer but to other preamplifiers and buffer circuit parts, in particular.
Alternatively, the bias potential of the substrate region (well region) of the p-channel MOS transistor in the memory cell array may be formed by the peripheral circuit source potential Vccp. When source lines transmitting different source potentials are arranged in the memory cell array, however, the area for laying out the source lines is increased and it is extremely difficult to arrange source lines transmitting different source potentials in an array part having a limited area.
When the array source potential and the peripheral circuit source potential are generated independently of each other as in the conventional semiconductor memory device, therefore, it is difficult to implement low current consumption by reducing the array source potential Vccp without reducing the access speed.
FIG. 33 schematically illustrates the structure of the output buffer.
Referring to FIG. 33, the output buffer 13 includes an n-channel MOS transistor OQ1 which is connected between an external source potential Vcc supply node and an output node NDQ, an n-channel MOS transistor OQ2 which is connected between the output node NDQ and another power supply node (ground node), a drive circuit ODa which receives internal read data /RO, generates a drive signal and supplies the same to the gate of the MOS transistor OQ1, and a drive circuit ODb which receives read data RO, generates a drive signal and supplies the same to the gate of the MOS transistor OQ2. The read data/RO and RO have the amplitude of the peripheral circuit source potential Vccp. The drive circuit ODa converts a low-level potential (the internal source potential Vccp) of the read data /RO to a potential Vcd. This drive circuit ODa is formed by a boosting circuit employing a charge pump capacitor or a level conversion circuit. A drive signal Vcd which is at a higher voltage level than the external source potential Vcc is applied to the gate of the MOS transistor OQ1, whereby a signal of the external source potential Vcc level can be transmitted to the output node NDQ with no loss of the threshold voltage of the MOS transistor OQ1.
The drive circuit ODb inverts a low level of the read data RO to a high level and converts the high-level signal to the external source potential Vcc level. This drive circuit ODb includes an inverter IV1 which receives the read data RO, a p-channel MOS transistor PQ1 which is connected between an external source potential supply node Vcc (nodes and potentials supplied thereto are denoted by the same symbols) and a node Na and has its gate connected to a node Nb, a p-channel MOS transistor PQ2 which is connected between the external source potential supply node Vcc and the node Nb and has its gate connected to the node Na, an n-channel MOS transistor NQ1 which is connected between the node Na and a ground node and has its gate connected to receive the read data RO, an n-channel MOS transistor NQ2 which is connected between the node Nb and the ground node and has its gate connected to receive the output signal of the inverter IV1, and an inverter IV2 which inverts a signal on the node Nb and supplies the inverted signal to the gate of the MOS transistor OQ2.
The inverter IV2 operates with the external source potential Vcc of 3 V, for example, which is supplied on the external source potential supply node Vcc, serving as a first operation source potential. In this drive circuit ODb, the MOS transistors NQ2 and NQ1 enter ON and OFF states respectively when the read signal RO is at a low level, and the node Nb is discharged to the ground potential level through the MOS transistor NQ2. In response to the lowering of the potential level of the node Nb, the MOS transistor PQ1 enters an ON state, the node Na is charged to the external source potential Vcc level, and the MOS transistor PQ2 is brought into an OFF state. Thus, the potential on the node Nb is fixed at the ground potential level, and the output signal of the inverter IV2 is converted to the external source potential Vcc level. The MOS transistor 0Q2 conducts in response to the high-level signal of the external source potential Vcc level from the inverter IV2, and discharges the node NDQ to the ground potential level.
The semiconductor memory device transfers data with an external device EX such as a CPU (central processing unit), for example. Elements forming the external device EX are not fined down (not highly integrated) as compared with the semiconductor memory device, and hence the external device EX cannot have the same source potential as the semiconductor memory device but a source potential of 5 V, for example, is utilized as that for the external device. A source potential of 3 V is utilized as the source potential Vcc of the semiconductor memory device, in order to maintain compatibility with an old generation semiconductor memory device having a source voltage which is not reduced.
The potential Vcd which is supplied to the gate of the MOS transistor OQ1 charging the output node NDQ is sufficiently higher than the external source potential Vcc, whereby the potential difference between the drain (node receiving the source potential) and the gate is small and hence the distance between a pinch-off point and the drain region is extremely small.
On the other hand, the potential of the gate of the MOS transistor OQ2 discharging the output node NDQ is 3 V, while the potential of its drain is 5 V. Thus, the gate potential is considerably lower than the drain potential. In this case, the discharging MOS transistor OQ2 is disadvantageously deteriorated. The mechanism of such deterioration is now described.
FIG. 34 schematically illustrates the sectional structure of the n-channel MOS transistor OQ2. Referring to FIG. 34, the MOS transistor OQ2 includes high concentration n-type impurity regions IRS and IRD which are formed on the surface of the p-type semiconductor substrate SUB, and a gate electrode layer GL which is formed on the surface of the substrate SUB between the impurity regions IRS and IRD with a gate insulating film (not shown) interposed therebetween. The impurity region IRS forms a source region, and is connected to a ground node S to receive a ground potential GND. The impurity region IRD forms a drain region, and is coupled to the output node NDQ for receiving a drain potential Vd of 5 V, for example. A gate potential Vg is applied to the gate electrode layer GL from the inverter IV2. The MOS transistor may cause such a pinch-off phenomenon that an inversion layer disappears in the channel region. This pinch-off phenomenon takes place when Vg-Vth=Vd, where Vth represents the threshold voltage of the MOS transistor. This pinch-off point (inversion layer disappearance point) moves toward the impurity region IRS forming a source. When the drain potential Vd exceeds a saturation potential (a voltage causing a pinch-off phenomenon, expressed as Vg-Vth), an inversion layer disappears in a region L, with presence of only a depletion layer. The voltage Vd which has been applied to the drain impurity region IRD is applied to this region L. When the gate potential Vg is lower than the drain potential Vd, i.e., when the gate potential Vg is 3 V and the drain potential Vd is 5 V as shown in FIG. 33, therefore, a pinch-off phenomenon is caused and the length of the region L to which a high electric field is applied is lengthened. In the region L to which a high electric field is applied, hot carriers are generated and holes are trapped in the gate insulating film, to deteriorate the characteristics of the gate insulating film and disadvantageously deteriorate dielectric breakdown immunity.
The drive circuit ODb has no function of converting the potential of its output signal to a higher level than the external source potential Vcc dissimilarly to the drive circuit ODa since the output discharging MOS transistor OQ2 is merely required to discharge the output node NDQ to the ground potential level and no problem of threshold voltage loss is caused in this case. Thus, the drive circuit ODb is simply provided with only a level conversion function, in consideration of the circuit occupied area and current consumption.